Double gated thin film transistors

ABSTRACT

Double gated thin film transistors are described. In an example, an integrated circuit structure includes an insulator layer above a substrate. A first gate electrode is on the insulator layer, the first gate electrode having a non-planar feature. A first gate dielectric is on and conformal with the non-planar feature of the first gate electrode. A channel material layer is on and conformal with the first gate dielectric. A second gate dielectric is on and conformal with the channel material layer. A second gate electrode is on and conformal with the second gate dielectric. A first source or drain region is coupled to the channel material layer at a first side of the first gate dielectric. A second source or drain region is coupled to the channel material layer at a second side of the first gate dielectric.

TECHNICAL FIELD

Embodiments of the disclosure are in the field of integrated circuit structures and, in particular, double gated thin film transistors.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.

For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yielding bulk silicon substrate infrastructure. Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

The performance of a thin-film transistor (TFT) may depend on a number of factors. For example, the efficiency at which a TFT is able to operate may depend on the sub threshold swing of the TFT, characterizing the amount of change in the gate-source voltage needed to achieve a given change in the drain current. A smaller sub threshold swing enables the TFT to turn off to a lower leakage value when the gate-source voltage drops below the threshold voltage of the TFT. The conventional theoretical lower limit at room temperature for the sub threshold swing of the TFT is 60 millivolts per decade of change in the drain current.

Variability in conventional and state-of-the-art fabrication processes may limit the possibility to further extend them into the, e.g. 10 nm or sub-10 nm range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a cross-sectional view of a single gate thin film transistor (TFT).

FIG. 1B illustrates a cross-sectional view of a double gate thin film transistor (TFT).

FIG. 2A illustrates a cross-sectional view of a double gated thin film transistor (TFT), as taken through a gate electrode fin and perpendicular to a current flow, in accordance with an embodiment of the present disclosure.

FIG. 2B illustrates a cross-sectional view of a first arrangement of a double gated thin film transistor (TFT) of the type of FIG. 2A, as taken along a gate electrode fin and parallel with a current flow, in accordance with an embodiment of the present disclosure.

FIG. 2C illustrates a cross-sectional view of a second arrangement of a double gated thin film transistor (TFT) of the type of FIG. 2A, as taken along a gate electrode fin and parallel with a current flow, in accordance with an embodiment of the present disclosure.

FIG. 3A illustrates a cross-sectional view taken along a gate “width” of a planar double gate thin film transistor (TFT).

FIG. 3B illustrates a cross-sectional view taken along a gate “width” of a non-planar double gated thin film transistor (TFT), in accordance with an embodiment of the present disclosure.

FIGS. 3C, 3D, and 3E illustrate angled and direct cross-sectional views of a non-planar double gated thin film transistor (TFT), in accordance with an embodiment of the present disclosure.

FIGS. 4A, 4B, and 4C illustrate angled and direct cross-sectional views of a non-planar double gated tunnel thin film transistor, in accordance with an embodiment of the present disclosure.

FIGS. 5A and 5B are top views of a wafer and dies that include one or more thin film transistors having double gates, in accordance with one or more of the embodiments disclosed herein.

FIG. 6 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more thin film transistors having double gates, in accordance with one or more of the embodiments disclosed herein.

FIG. 7 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more thin film transistors having double gates, in accordance with one or more of the embodiments disclosed herein.

FIG. 8 illustrates a computing device in accordance with one implementation of an embodiment of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

Double gated thin film transistors are described. In the following description, numerous specific details are set forth, such as specific material and tooling regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper”, “lower”, “above”, “below,” “bottom,” and “top” refer to directions in the drawings to which reference is made. Terms such as “front”, “back”, “rear”, and “side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL.

Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

One or more embodiments described herein are directed to structures and architectures for fabricating BEOL double gated thin film transistors (TFTs), such as double gated trigate-like thin film devices. Embodiments may include or pertain to one or more of back end transistors, thin film transistors, system-on-chip (SoC) technologies, and embedded dynamic random access memory (eDRAM) technologies. One or more embodiments may be implemented to realize high performance backend transistors to potentially increase monolithic integration of backend logic plus memory in SoCs of future technology nodes. Embodiments described herein may be implemented to provide double gated TFTs for improved gate control. Double gated transistors described herein may be implemented as eDRAM access transistors.

In accordance with one or more embodiments of the present disclosure, a double-gated tri-gate thin film transistor is described. Such an architecture may provide for devices which are efficient in terms of area usage. A double gate aspect may enable the devices to operate at multiple or tunable threshold voltages and with performance which can be optimized for either low leakage or high speed switching.

To provide context, common implementations of TFT devices utilize a planar implementation of the device with a single gate. Such implementations are less area efficient and do not provide the benefits that a double gate device provide (e.g., threshold voltage control and low leakage/high speed tradeoff). To provide further context, thin film transistors having a relatively thick body may not exhibit good electrostatic gate control. Furthermore, a passivation layer on a top of a TFT may cause interactions leading to undesirable doping which may increase OFF-state leakage and degrade subthreshold swing of a TFT device. In accordance with one or more embodiments of the present disclosure, a second gate is introduced on a top of a channel material layer of a TFT in order to control the channel closest to the top interface. Such embodiments may be implemented to improve overall electrostatics and ON/OFF ratio for the TFT device.

For comparative purposes, FIG. 1A illustrates a cross-sectional view of a single gate thin film transistor (TFT).

Referring to FIG. 1A, an integrated circuit structure 100 includes a thin film transistor (TFT) 102 fabricated on an insulator layer 104. A gate stack is on the insulator layer 104, the gate stack including a gate electrode 106 and a gate dielectric layer 108. A channel material layer 110 is on the gate stack 106/108. An insulating capping layer 112 is on a first portion of the channel material layer 110, the insulating capping layer 112 having a first side opposite a second side. The insulating capping layer 112 may be recessed into the channel material layer 110, as is depicted. A first conductive contact 114 is adjacent the first side of the capping layer 112, the first conductive contact 114 on a second portion of the channel material layer 110. A second conductive contact 116 is adjacent the second side of the capping layer 112, the second conductive contact 116 on a third portion of the channel material layer 110.

To improve control and performance of the TFT of FIG. 1, a second gate stack may be implemented. As an example, FIG. 1B illustrates a cross-sectional view of a double gate thin film transistor (TFT).

Referring to FIG. 1B, an integrated circuit structure 150 includes a thin film transistor (TFT) 152 fabricated on an insulator layer 154, which may be an inter-layer dielectric (ILD) layer above a substrate. A first gate stack is on the insulator layer 154, the first gate stack including a first gate electrode 156 and a first gate dielectric layer 158. A channel material layer 160 is on the first gate stack 156/158. A second gate stack is on a first portion of the channel material layer 160, the second gate stack including a second gate electrode 166 and a second gate dielectric layer 168. The second gate stack 166/168 has a first side opposite a second side, and may be recessed into the channel material layer 160, as is depicted. A first conductive contact 162 is adjacent the first side of the second gate stack 166/168, the first conductive contact 162 on a second portion of the channel material layer 160. A second conductive contact 164 is adjacent the second side of the second gate stack 166/168, the second conductive contact 164 on a third portion of the channel material layer 160.

In accordance with one or more embodiment of the present disclosure, a three-dimensional metal template formed upon a wafer substrate is utilized as a bottom gate electrode or bottom gate electrode portion of a double gated TFT. A first gate dielectric, a channel material, and a second gate dielectric are formed over the three-dimensional metal template. A second gate electrode is then formed over the resulting structure. The bottom gate electrode and the second gate electrode may be operated independently in order to dynamically adjust the threshold voltage and leakage current of the device. Advantages of implementing embodiments described herein may include providing for reduced leakage power and efficient high density device integration.

As an exemplary architecture, FIG. 2A illustrates a cross-sectional view of a double gated thin film transistor (TFT), as taken through a gate electrode fin and perpendicular to a current flow, in accordance with an embodiment of the present disclosure. FIG. 2B illustrates a cross-sectional view of a first arrangement of a double gated thin film transistor (TFT) of the type of FIG. 2A, as taken along a gate electrode fin and parallel with a current flow, in accordance with an embodiment of the present disclosure. FIG. 2C illustrates a cross-sectional view of a second arrangement of a double gated thin film transistor (TFT) of the type of FIG. 2A, as taken along a gate electrode fin and parallel with a current flow, in accordance with an embodiment of the present disclosure.

Referring to FIGS. 2A, 2B and 2C, an integrated circuit structure 200 includes an insulator layer 204 above a substrate 200. A first gate electrode 212′/215 is on the insulator layer 204, the first gate electrode 212′/215 having a non-planar feature 215. A first gate dielectric 214′ is on and conformal with the non-planar feature 215 of the first gate electrode 212′/215. A channel material layer 206 is on and conformal with the first gate dielectric 214′. A second gate dielectric 214 is on and conformal with the channel material layer 206. A second gate electrode 212 is on and conformal with the second gate dielectric 214. Referring to FIGS. 2B and 2C, a first source or drain region (left 212) is coupled to the channel material layer 206 at a first side of the first gate dielectric 214′. A second source or drain region (right 212) is coupled to the channel material layer 206 at a second side of the first gate dielectric 214′.

In an embodiment, the bottom gate non-planar feature 215 is a fin. It is to be appreciated that other geometries may be used. Also, non-planar feature 215 is depicted as a cuboid geometry. In practice, the bottom gate may have non-orthogonal angles, curved surfaces or other features differing from a cuboid. For a non-cuboid bottom gate, in one embodiment, the gate dielectric and TFT layers are conformal to the shape of the bottom gate. In an embodiment, the gate electrode fin 215 has squared-off (as shown) or rounded corners, and has vertical (as shown) or sloped sidewalls. In an embodiment, the first gate electrode 212′/215 extends beyond the non-planar feature 215 along the insulator layer 204. In one such embodiment, a second insulator layer 213 is on the portion of the first gate electrode 212′/215 that extends beyond the non-planar feature 215 along the insulator layer 204. The second insulator layer 213 is between the second gate electrode 212 and the portion of the first gate electrode 212′/215 that extends beyond the non-planar feature 215 along the insulator layer 204.

In an embodiment, the first gate electrode 212′/215 is electrically independent from the second gate electrode 212, e.g., they do not share a common contact or interconnect. In another embodiment, the first gate electrode 212′/215 is electrically coupled to the second gate electrode 212, e.g., they may share a common contact or interconnect. It is to be appreciated that contact to the first or bottom gate electrode 212′/215 may be formed from beneath (e.g., such as in the case of a stacked transistor architecture) or from above (e.g., such as from a wrap-around contact). It is also to be appreciated that multiple bottom or top gates from multiple transistor assemblies may be tied together at a same voltage/potential. Such an arrangement allows for entire circuit blocks to alter their switching behavior dynamically. In such a manner, a circuit block may be put into a “sleep” or low-leakage/standby state.

In an embodiment, the first and second source or drain regions 252 are continuous with the channel material layer 206, as is depicted in FIGS. 2B and 2C. In a specific such embodiment, the first and second source or drain regions 252 are larger/wider than the TFT region in the channel 206 which may provide for an improved contact at the first and second source or drain regions 252. In an embodiment, channel material layer 206 includes a semiconducting oxide material. In another embodiment, channel material layer 206 includes polycrystalline silicon.

In another embodiment, although not depicted as such, a portion of or the entirety of first and second source or drain regions 252 drain is replaced by a metal region or partially replaced by a metal region. In one such embodiment, a portion of first and second source or drain regions 252 include a metal at a distance from gate the gate electrode.

In an embodiment, bottom and top channel lengths of an integrated circuit structure such as structure 200 are different from one another. Such a difference may be implemented intentionally or as the result of variations in processing. Similarly, the bottom gate may not be centered about the midpoint of the top gate. Additional process variations may include different gate dielectric thicknesses or compositions for the top and bottom gate and different metals used in the top and bottom gate stacks.

In one exemplary embodiment, referring to FIG. 2B, the second gate electrode 212 has a lateral width between the first source or drain region (left 212) and the second source or drain region (right 212) the same as a lateral width of the first gate electrode 212′/215 between the first source or drain region (left 212) and the second source or drain region (right 212). In another exemplary embodiment, referring to FIG. 2C, the second gate electrode 212 has a lateral width between the first source or drain region (left 212) and the second source or drain region (right 212) greater than a lateral width of the first gate electrode 212′/215 between the first source or drain region (left 212) and the second source or drain region (right 212). In yet another embodiment, although not depicted, the second gate electrode has a lateral width between the first source or drain region and the second source or drain region less than a lateral width of the first gate electrode between the first source or drain region and the second source or drain region.

In another aspect, one or more embodiments described herein are directed to structures and architectures for fabricating BEOL thin film transistors (TFTs) having relatively increased width relative to TFTs of conventional geometry. One or more embodiments may be implemented to realize high performance backend transistors and to potentially enhance monolithic integration of backend logic plus memory in SoCs of future technology nodes.

To provide context, there is increased need for advanced SoCs to include monolithically integrated BEOL transistors for logic functionality at higher metal layers. Such BEOL transistors typically have a lower thermal budget than front end transistors due to increased thermal sensitivity of backend materials. Also, the performance of such transistors may be severely hampered due to low channel mobility for BEOL-compatible channel materials such as IGZO (indium gallium zinc oxide).

In accordance with one or more embodiments described herein, non-planar BEOL-compatible double gated thin film transistors (TFTs) are fabricated by effectively increasing the transistor width (and hence the drive strength and performance) for a given projected area. A double gated TFT fabricated using such an architecture may exhibit an increase in gate control, stability, and performance of thin film transistors. Applications of such systems may include, but are not limited to, back end (BEOL) logic, memory, or analog applications. Embodiments described herein may include non-planar structures that effectively increase transistor width (relative to a planar device) by integrating the devices in unique architectures.

To provide a benchmark, FIG. 3A illustrates a cross-sectional view taken along a gate “width” of a planar double gate thin film transistor (TFT).

Referring to FIG. 3A, a planar double gated TFT 300 is formed above a substrate 302, e.g., on an insulating layer 304 above a substrate, as is shown. The planar double gated TFT 300 includes a channel material 306. An upper gate electrode 308 is formed on a gate dielectric layer 314 formed on the channel material 306. The upper gate electrode 308 may include a fill material 310 on a workfunction layer 312, as is depicted. The upper gate electrode 308 may expose regions 316 of the channel material 306 and the gate dielectric layer 314, as is depicted. Alternatively, the channel material 306 and the gate dielectric layer 314 have a same lateral dimension as the gate electrode 308. A lower gate electrode 312′ is on the insulating layer 304 below the channel material 306. A gate dielectric layer 314′ is between the channel material 306 and the lower gate electrode 312′. It is to be appreciated that source or drain regions are into and out of the page of the view of FIG. 3A.

The planar double gated TFT 300 has an effective gate width that is the length of the planar channel material 306 between locations A and B, as depicted in FIG. 3A. By contrast, as a first example of a structure having a relative increase in transistor width (e.g., relative to the structure of FIG. 3A), FIG. 3B illustrates a cross-sectional view taken along a gate “width” of a non-planar double gated thin film transistor (TFT), in accordance with an embodiment of the present disclosure.

Referring to FIG. 3B, a non-planar double gated TFT 350 is formed above a substrate 352, e.g., on an insulating layer 354 above a substrate, as is shown. The non-planar double gated TFT 350 includes a channel material layer 356, such as a semiconducting oxide material or polycrystalline silicon. The channel material layer 356 is conformal with a lower non-planar gate stack. The lower gate stack includes gate electrode 362′ and gate dielectric layer 364′. Gate electrode 362′ includes a pair of gate electrode fins 355. In an embodiment, individual one of the plurality of fins 355 is continuous with one another, as is depicted. An upper gate electrode 358 is on an upper gate dielectric layer 364 on the channel material layer 356. The upper gate electrode 358 may include a fill material 360 on a workfunction layer 362, as is depicted. The upper gate electrode 358 may expose regions 366 of the channel material layer 356 and the gate dielectric layer 364, as is depicted. Alternatively, the channel material layer 356 and the gate dielectric layer 364 have a same lateral dimension as the gate electrode 358.

In an embodiment, the gate dielectric layers 364 and 364′ are composed of a same material. In an embodiment, gate electrodes 362 and 362′ are composed of a same material. It is to be appreciated that source or drain regions are into and out of the page of the view of FIG. 3B. In an embodiment, a first source or drain region is coupled to the channel material layer 356 at a first side of gate electrode 358. A second source or drain region is coupled to the channel material layer 356 at a second side of the gate electrode 358.

The non-planar double gated TFT 350 has an effective gate width that is the length of the conformal semiconducting oxide material 356 between locations A′ and B′, i.e., the full length including undulating portions over the tops and sidewalls of the gate electrode fins 355, as is depicted in FIG. 3B. In comparison to FIG. 3A, the structure of FIG. 3B highlights the advantage of a non-planar architecture to increase effective gate width, referred to herein as a relatively increased width.

In an embodiment, gate electrode fins described herein may be fabricated as a grating structure, where the term “grating” is used herein to refer to a tight pitch grating structure that has two or more of the above described gate electrode fins. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, a grating-like patterns described herein may have gate electrode fins spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach. In an embodiment, the gate electrode fin or fins 355 each have squared-off (as shown) or rounded corners, and each have vertical (as shown) or sloped sidewalls.

To highlight other aspects of a non-planar double gated TFT topography, FIGS. 3C, 3D (taken at gate cut along a-axis), and 3E (taken at insulating fin cut along b-axis) illustrate angled and direct cross-sectional views of a non-planar double gated thin film transistor (TFT), in accordance with an embodiment of the present disclosure. It is to be appreciated that one gate electrode fin is illustrated in FIGS. 3C-3E for simplification. Embodiments may include a single device fabricated over one (FIG. 3C), two (FIG. 3B) or more such gate electrode fins.

Referring to FIGS. 3C, 3D and 3E, an integrated circuit structure 370 includes an insulator layer 354 above a substrate 352. A first gate stack 362′/364′ is on the insulator layer 354. The first gate stack 362′/364′ includes a first gate electrode 362′ and a first gate dielectric 364′. The first gate electrode 362′ includes a gate electrode fin 355, and the first gate dielectric 364′ is conformal with the gate electrode fin 355. A channel material layer 356, such as a semiconducting oxide material or polycrystalline silicon, is on and conformal with the first gate stack 362′/364′. A second gate stack 362/364 is on a first portion of the channel material layer 356, the second gate stack 362/364 having a first side (front or left) opposite a second side (back or right). The second gate stack 362/364 includes a second gate electrode 362 and a second gate dielectric 364. A first conductive contact (front or left 374) is adjacent the first side of the second gate stack 362/364, the first conductive contact (front or left 374) on a second portion of the channel material layer 356. A second conductive contact (back or right 374) is adjacent the second side of the second gate stack 362/364, the second conductive contact (back or right 374) on a third portion of the channel material layer 356.

In an embodiment, as shown, a gate electrode 362′ of the first gate stack 362′/364′ is electrically independent from a gate electrode 362 of the second gate stack 362/364. In another embodiment, a gate electrode 362′ of the first gate stack 362′/364′ is electrically coupled to a gate electrode 362 of the second gate stack 362/364, e.g., they may share a common contact or interconnect (not shown). In an embodiment, gate electrodes 362 and 362′ are or include metal gate electrodes.

In an embodiment, the integrated circuit structure 370 further includes a first dielectric spacer (front or left 372) between the first conductive contact (front or left 374) and the first side of the second gate stack 362/364. The first dielectric spacer (front or left 372) is over a fourth portion of the channel material layer 356. A second dielectric spacer (back or right 372) is between the second conductive contact (back or right 374) and the second side of the second gate stack 362/364. The second dielectric spacer (back or right 372) is over a fifth portion of the channel material layer 356.

In accordance with an embodiment of the present disclosure, the above TFT double gated non-planar architectures 350 and 370 provide for higher effective widths for a transistor for a scaled projected area. In an embodiment, the drive strength and performance of such transistors are improved over state-of-the-art planar BEOL transistors.

In another aspect, in accordance with one or more embodiment of the present disclosure, three dimensional (3D) double gated tunnel field effect transistors (TFETs) having increased gate width are described. Such TFETs may be implemented for use in one transistor-one resistive memory (1T-1R, or 1T1R) memory cells for embedded non-volatile memory (eNVM) applications.

To provide context, it is to be appreciated that conventional transistors often require high voltages to write the memory in 1T1R arrangements. Such a requirement may be challenging for low Vcc eNVM. A tunnel-FET can accommodate for such Vcc issues, but the drive current is typically low. In accordance with one or more embodiments described herein, addressing one or more of the above issues, a three-dimensional (3D) double gated tunnel FET is described. The 3D double gated tunnel FET may be used as a selector for eNVM applications. In an embodiment, a 3D double gated tunnel FET described herein has high drive due to increased gate width relative to a counterpart planar device.

FIGS. 4A, 4B (taken at gate cut along a-axis), and 4C (taken at insulating fin cut along b-axis) illustrate angled and direct cross-sectional views of a non-planar double gated tunnel thin film transistor, in accordance with an embodiment of the present disclosure. It is to be appreciated that one gate electrode fin is illustrated in FIGS. 4A-4C for simplification. Embodiments may include a single device fabricated over one, two or more such gate electrode fins.

Referring to FIGS. 4A, 4B and 4C, an integrated circuit structure 470 includes an insulator layer 454 above a substrate 452. A first gate stack 462′/464′ is on and conformal with the insulator structure 454/455. The first gate stack 462′/464′ includes a first gate electrode 462′ and a first gate dielectric 464′. The first gate electrode 462′ includes a gate electrode fin 455, and the first gate dielectric 464′ is conformal with the gate electrode fin 455. A channel material layer 456, such as a semiconducting oxide material or polycrystalline silicon, is on and conformal with the first gate stack 462′/464′. A second gate stack 462/464 is on a channel portion of the channel material layer 456, the second gate stack 462/464 having a first side (front or left) opposite a second side (back or right). The second gate stack 462/464 includes a second gate electrode 462 and a second gate dielectric 464. A first conductive contact (front or left 474) is adjacent the first side of the second gate stack 462/464, the first conductive contact (front or left 474) on a source portion 497 of the channel material layer 456. The source 497 portion 497 of the channel material layer 456 has a first conductivity type. A second conductive contact (back or right 474) is adjacent the second side of the second gate stack 462/464, the second conductive contact (back or right 474) on a drain portion 499 of the channel material layer 456. The drain portion 499 of the channel material layer 456 has a second conductivity type opposite the first conductivity type.

In an embodiment, the source portion 497 of the channel material layer 456 is a p-type doped portion (e.g., a boron-doped portion of a polycrystalline silicon layer), and the drain portion 499 of the channel material layer 456 is an n-type doped portion (e.g., a phosphorus-doped portion or an arsenic-doped portion of a polycrystalline silicon layer). In another embodiment, the source portion 497 of the channel material layer 456 is an n-type doped portion (e.g., a phosphorus-doped portion or an arsenic-doped portion of a polycrystalline silicon layer), and the drain portion 499 of the channel material layer 456 is a p-type doped portion (e.g., a boron-doped portion of a polycrystalline silicon layer). In one embodiment, an intrinsic or lightly doped region 498 is between the source portion 497 of the channel material layer 456 and the drain portion 499 of the channel material layer 456.

In an embodiment, as shown, gate electrode 462′ of the first gate stack 462′/464′ is electrically independent from gate electrode 462 of the second gate stack 462/464. In another embodiment, gate electrode 462′ of the first gate stack 462′/464′ is electrically coupled to gate electrode 462 of the second gate stack 462/464, e.g., they may share a common contact or interconnect (not shown). In an embodiment, gate electrodes 462 and 462′ are or include metal gate electrodes.

In an embodiment, the integrated circuit structure 470 further includes a first dielectric spacer (front or left 472) between the first conductive contact (front or left 474) and the first side of the second gate stack 462/464. The first dielectric spacer (front or left 472) is over a fourth portion of the channel material layer 456. A second dielectric spacer (back or right 472) is between the second conductive contact (back or right 474) and the second side of the second gate stack 462/464. The second dielectric spacer (back or right 472) is over a fifth portion of the channel material layer 456.

It is to be appreciated that in some embodiments the layers and materials described in association with embodiments herein are formed on or above an underlying semiconductor substrate, e.g., as FEOL layer(s). In other embodiments, the layers and materials described in association with embodiments herein are formed on or above underlying device layer(s) of an integrated circuit, e.g., as BEOL layer(s) above an underlying semiconductor substrate. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, although not depicted, structures described herein may be fabricated on underlying lower level back end of line (BEOL) interconnect layers.

In the case that an insulator layer 204, 354 or 454 is optionally used, the insulator layer 204, 354 or 454 may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a gate structure from an underlying bulk substrate or interconnect layer. For example, in one embodiment, the insulator layer 204, 354 or 454 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride. In a particular embodiment, the insulator layer 204, 354 or 454 is a low-k dielectric layer of an underlying BEOL layer.

In an embodiment, the channel material layer 206, 356 or 456 of a double gated TFT includes an IGZO layer that has a gallium to indium ratio of 1:1, a gallium to indium ratio greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), or a gallium to indium ratio less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9, or 1:10). A low indium content IGZO may refer to IGZO having more gallium than indium (e.g., with a gallium to indium ratio greater than 1:1), and may also be referred to as high gallium content IGZO. Similarly, low gallium content IGZO may refer to IGZO having more indium than gallium (e.g., with a gallium to indium ratio less than 1:1), and may also be referred to as high indium content IGZO. In another embodiment, the channel material layer 206, 356 or 456 is or includes a material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In another embodiment, polycrystalline silicon is used as the channel material 206, 356 or 456 instead of a semiconducting oxide material. In an embodiment, no matter the composition, the channel material layer 206, 356 or 456 has a thickness between 5 nanometers and 30 nanometers. In another embodiment, the channel material layer 206, 356 or 456 of a double gated TFT includes an oxide semiconductors such as, but not limited to, SnO, SnO₂, Cu₂O, CoO, ZnO, Ga₂O₃, IZO, ITO, AZO, or TiO₂. In another embodiment, the channel material layer 206, 356 or 456 of a double gated TFT includes a material such as, but not limited to, poly-Si, poly-SiGe, poly-Ge, poly-III-V, BeTe, or other tellurides.

In an embodiment, the channel material layer 206, 356 or 456 is an amorphous, crystalline, or semi crystalline oxide semiconductor, such as an amorphous, crystalline, or semi crystalline oxide semiconductor IGZO layer. The semiconducting oxide material may be formed using a low-temperature deposition process, such as physical vapor deposition (PVD) (e.g., sputtering), atomic layer deposition (ALD), or chemical vapor deposition (CVD). The ability to deposit the semiconducting oxide material at temperatures low enough to be compatible with back-end manufacturing processes represents a particular advantage. The semiconducting oxide material may be deposited on sidewalls or conformably on any desired structure to a precise thickness, allowing the manufacture of transistors having any desired geometry.

In an embodiment, gate electrodes, including gate electrode fins, described herein include at least one P-type work function metal or N-type work function metal, depending on whether the integrated circuit device 200, 350, 370 or 470 is to be included in a P-type transistor or an N-type transistor. For a P-type transistors, metals that may be used for the gate electrode may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an N-type transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In one embodiment, a metal gate electrode of a P-type transistor includes nickel oxide (NiO). In some embodiments, the gate electrode includes a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as to act as a barrier layer. In some implementations, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In an embodiment, gate dielectric layers described herein are composed of a high-K material. For example, in one embodiment, a gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. In some implementations, the gate dielectric may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate, as is depicted in FIGS. 3C, 3E, 4A and 4C.

In an embodiment, dielectric spacers are formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used. For example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate electrode.

In an embodiment, conductive contacts act as contacts to source or drain regions of a double gated TFT, or act directly as source or drain regions of the double gated TFT. The conductive contacts may be spaced apart by a distance that is the gate length of the transistor 200, 350, 370 or 470. In some embodiments, the gate length is between 7 and 30 nanometers. In an embodiment, the conductive contacts include one or more layers of metal and/or metal alloys. In a particular embodiment, the conductive contacts are composed of aluminum or an aluminum-containing alloy.

In an embodiment, interconnect lines (and, possibly, underlying via structures), such as interconnect lines, described herein are composed of one or more metal or metal-containing conductive structures. The conductive interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, interconnect lines or simply interconnects. In a particular embodiment, each of the interconnect lines includes a barrier layer and a conductive fill material. In an embodiment, the barrier layer is composed of a metal nitride material, such as tantalum nitride or titanium nitride. In an embodiment, the conductive fill material is composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof

In an embodiment, inter-layer dielectric (ILD) materials described herein are composed of or include a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO₂)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In one aspect, a gate electrode and gate dielectric layer, particularly upper gate stacks, may be fabricated by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF₆. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH₄OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.

In an embodiment, one or more approaches described herein contemplate essentially a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structures described herein. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature anneal of at least a portion of the permanent gate stack. For example, in a specific such embodiment, an anneal of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed. The anneal is performed prior to formation of the permanent contacts.

It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. For example, in one embodiment, dummy gates need not ever be formed prior to fabricating gate contacts over active portions of the gate stacks. The gate stacks described above may actually be permanent gate stacks as initially formed. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. One or more embodiments may be particularly useful for fabricating semiconductor devices at a 10 nanometer (10 nm) or smaller technology node.

In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193 nm immersion lithography (i193), extreme ultra-violet (EUV) and/or electron beam direct write (EBDW) lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

In another aspect, the performance of a thin film transistor (TFT) may depend on the carrier mobility of the components in the TFT. For example, a material with a higher carrier mobility enables carriers to move more quickly in response to a given electric field than a material with a lower carrier mobility. Accordingly, high carrier mobilities may be associated with improved performance. Although shown and described above as single semiconducting oxide layers, in accordance with embodiments described herein, a layer of a semiconducting oxide, such as a layer of IGZO, is between a high-k gate dielectric material and a higher mobility semiconducting oxide channel material. Although IGZO has a relatively low mobility (approximately 10 cm²/V-s), the sub threshold swing of IGZO may be close to the conventional theoretical lower limit. In some embodiments, a thin layer of IGZO may directly border a channel material of choice, and may be sandwiched between the channel material and the high-k dielectric. The use of IGZO at the interface between the gate stack and the channel may achieve one or more of a number of advantages. For example, an IGZO interface may have a relatively small number of interface traps, defects at which carriers are trapped and released that impede performance. A TFT that includes an IGZO layer as a second semiconducting oxide material may exhibit desirably low gate leakage. When IGZO is used as an interface to a non-IGZO semiconducting oxide channel material (e.g., a thin film oxide semiconductor material having a higher mobility than IGZO), the benefits of the higher mobility channel material may be realized simultaneously with the good gate oxide interface properties provided by the IGZO. In accordance with one or more embodiments described herein, a gate-channel arrangement based on a dual semiconducting oxide layer channel enables the use of a wider array of thin film transistor channel materials, while achieving desirable gate control, than realizable using conventional approaches.

In an embodiment, the addition of a second thin film semiconductor around a first TFT material can provide one or more of mobility enhancement, improved short channel effects (SCEs) particularly if all conduction occurs in the second material. The second TFT material may be selected for strong oxygen bond capability in order to stabilize the TFT when exposed to downstream processing. In accordance with one embodiment, a higher mobility semiconducting oxide material is effectively wrapped in a lower mobility material semiconducting oxide that is more oxygen stable. The resulting structure may limit the negative effects of downstream high temperature processing operations or aggressive operations on the inner TFT material by having the highly stable outer material. An increased set of materials that can be chosen to maximize stability and mobility simultaneously may be achieved using such a dual material architecture.

In another aspect, the integrated circuit structures described herein may be included in an electronic device. As a first example of an apparatus that may include one or more of the TFTs disclosed herein, FIGS. 5A and 5B are top views of a wafer and dies that include one or more thin film transistors having double gates, in accordance with any of the embodiments disclosed herein.

Referring to FIGS. 5A and 5B, a wafer 500 may be composed of semiconductor material and may include one or more dies 502 having integrated circuit (IC) structures formed on a surface of the wafer 500. Each of the dies 502 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more structures such as structures 200, 350, 370 or 470). After the fabrication of the semiconductor product is complete (e.g., after manufacture of structures 200, 350, 370 or 470), the wafer 500 may undergo a singulation process in which each of the dies 502 is separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include TFT as disclosed herein may take the form of the wafer 500 (e.g., not singulated) or the form of the die 502 (e.g., singulated). The die 502 may include one or more transistors and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 500 or the die 502 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 502. For example, a memory array formed by multiple memory devices may be formed on a same die 502 as a processing device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG. 6 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more thin film transistors having double gates, in accordance with one or more of the embodiments disclosed herein.

Referring to FIG. 6, an IC device 600 is formed on a substrate 602 (e.g., the wafer 500 of FIG. 5A) and may be included in a die (e.g., the die 502 of FIG. 5B), which may be singulated or included in a wafer. Although a few examples of materials from which the substrate 602 may be formed are described above, any material that may serve as a foundation for an IC device 600 may be used.

The IC device 600 may include one or more device layers, such as device layer 604, disposed on the substrate 602. The device layer 604 may include features of one or more transistors 640 (e.g., TFTs described above) formed on the substrate 602. The device layer 604 may include, for example, one or more source and/or drain (S/D) regions 620, a gate 622 to control current flow in the transistors 640 between the S/D regions 620, and one or more S/D contacts 624 to route electrical signals to/from the S/D regions 620. The transistors 640 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 640 are not limited to the type and configuration depicted in FIG. 6 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include Fin-based transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors. In particular, one or more of the transistors 640 take the form of the transistors 200, 350, 370 or 470. Thin-film transistors such as 200, 350, 370 or 470 may be particularly advantageous when used in the metal layers of a microprocessor device for analog circuitry, logic circuitry, or memory circuitry, and may be formed along with existing complementary metal oxide semiconductor (CMOS) processes.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 640 of the device layer 604 through one or more interconnect layers disposed on the device layer 604 (illustrated in FIG. 6 as interconnect layers 606-610). For example, electrically conductive features of the device layer 604 (e.g., the gate 622 and the S/D contacts 624) may be electrically coupled with the interconnect structures 628 of the interconnect layers 606-610. The one or more interconnect layers 606-610 may form an interlayer dielectric (ILD) stack 619 of the IC device 600.

The interconnect structures 628 may be arranged within the interconnect layers 606-610 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 628 depicted in FIG. 6). Although a particular number of interconnect layers 606-610 is depicted in FIG. 6, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures 628 may include trench structures 628 a (sometimes referred to as “lines”) and/or via structures 628 b filled with an electrically conductive material such as a metal. The trench structures 628 a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 602 upon which the device layer 604 is formed. For example, the trench structures 628 a may route electrical signals in a direction in and out of the page from the perspective of FIG. 6. The via structures 628 b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 602 upon which the device layer 604 is formed. In some embodiments, the via structures 628 b may electrically couple trench structures 628 a of different interconnect layers 606-610 together.

The interconnect layers 606-610 may include a dielectric material 626 disposed between the interconnect structures 628, as shown in FIG. 6. In some embodiments, the dielectric material 626 disposed between the interconnect structures 628 in different ones of the interconnect layers 606-610 may have different compositions; in other embodiments, the composition of the dielectric material 626 between different interconnect layers 606-610 may be the same. In either case, such dielectric materials may be referred to as inter-layer dielectric (ILD) materials.

A first interconnect layer 606 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 604. In some embodiments, the first interconnect layer 606 may include trench structures 628 a and/or via structures 628 b, as shown. The trench structures 628 a of the first interconnect layer 606 may be coupled with contacts (e.g., the S/D contacts 624) of the device layer 604.

A second interconnect layer 608 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 606. In some embodiments, the second interconnect layer 608 may include via structures 628 b to couple the trench structures 628 a of the second interconnect layer 608 with the trench structures 628 a of the first interconnect layer 606. Although the trench structures 628 a and the via structures 628 b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 608) for the sake of clarity, the trench structures 628 a and the via structures 628 b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

A third interconnect layer 610 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 608 according to similar techniques and configurations described in connection with the second interconnect layer 608 or the first interconnect layer 606.

The IC device 600 may include a solder resist material 634 (e.g., polyimide or similar material) and one or more bond pads 636 formed on the interconnect layers 606-610. The bond pads 636 may be electrically coupled with the interconnect structures 628 and configured to route the electrical signals of the transistor(s) 640 to other external devices. For example, solder bonds may be formed on the one or more bond pads 636 to mechanically and/or electrically couple a chip including the IC device 600 with another component (e.g., a circuit board). The IC device 600 may have other alternative configurations to route the electrical signals from the interconnect layers 606-610 than depicted in other embodiments. For example, the bond pads 636 may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG. 7 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more thin film transistors having double gates, in accordance with one or more of the embodiments disclosed herein.

Referring to FIG. 7, an IC device assembly 700 includes components having one or more integrated circuit structures described herein. The IC device assembly 700 includes a number of components disposed on a circuit board 702 (which may be, e.g., a motherboard). The IC device assembly 700 includes components disposed on a first face 740 of the circuit board 702 and an opposing second face 742 of the circuit board 702. Generally, components may be disposed on one or both faces 740 and 742. In particular, any suitable ones of the components of the IC device assembly 700 may include a number of the TFT structures 200, 350, 370 or 470 disclosed herein.

In some embodiments, the circuit board 702 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 702. In other embodiments, the circuit board 702 may be a non-PCB substrate.

The IC device assembly 700 illustrated in FIG. 7 includes a package-on-interposer structure 736 coupled to the first face 740 of the circuit board 702 by coupling components 716. The coupling components 716 may electrically and mechanically couple the package-on-interposer structure 736 to the circuit board 702, and may include solder balls (as shown in FIG. 7), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure 736 may include an IC package 720 coupled to an interposer 704 by coupling components 718. The coupling components 718 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 716. Although a single IC package 720 is shown in FIG. 7, multiple IC packages may be coupled to the interposer 704. It is to be appreciated that additional interposers may be coupled to the interposer 704. The interposer 704 may provide an intervening substrate used to bridge the circuit board 702 and the IC package 720. The IC package 720 may be or include, for example, a die (the die 502 of FIG. 5B), an IC device (e.g., the IC device 600 of FIG. 6), or any other suitable component. Generally, the interposer 704 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 704 may couple the IC package 720 (e.g., a die) to a ball grid array (BGA) of the coupling components 716 for coupling to the circuit board 702. In the embodiment illustrated in FIG. 7, the IC package 720 and the circuit board 702 are attached to opposing sides of the interposer 704. In other embodiments, the IC package 720 and the circuit board 702 may be attached to a same side of the interposer 704. In some embodiments, three or more components may be interconnected by way of the interposer 704.

The interposer 704 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 704 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 704 may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 706. The interposer 704 may further include embedded devices 714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 704. The package-on-interposer structure 736 may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly 700 may include an IC package 724 coupled to the first face 740 of the circuit board 702 by coupling components 722. The coupling components 722 may take the form of any of the embodiments discussed above with reference to the coupling components 716, and the IC package 724 may take the form of any of the embodiments discussed above with reference to the IC package 720.

The IC device assembly 700 illustrated in FIG. 7 includes a package-on-package structure 734 coupled to the second face 742 of the circuit board 702 by coupling components 728. The package-on-package structure 734 may include an IC package 726 and an IC package 732 coupled together by coupling components 730 such that the IC package 726 is disposed between the circuit board 702 and the IC package 732. The coupling components 728 and 730 may take the form of any of the embodiments of the coupling components 716 discussed above, and the IC packages 726 and 732 may take the form of any of the embodiments of the IC package 720 discussed above. The package-on-package structure 734 may be configured in accordance with any of the package-on-package structures known in the art.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

FIG. 8 illustrates a computing device 800 in accordance with one implementation of the disclosure. The computing device 800 houses a board 802. The board 802 may include a number of components, including but not limited to a processor 804 and at least one communication chip 806. The processor 804 is physically and electrically coupled to the board 802. In some implementations the at least one communication chip 806 is also physically and electrically coupled to the board 802. In further implementations, the communication chip 806 is part of the processor 804.

Depending on its applications, computing device 800 may include other components that may or may not be physically and electrically coupled to the board 802. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 806 enables wireless communications for the transfer of data to and from the computing device 800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 806 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 800 may include a plurality of communication chips 806. For instance, a first communication chip 806 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 806 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 804 of the computing device 800 includes an integrated circuit die packaged within the processor 804. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more thin film transistors having double gates, in accordance with implementations of embodiments of the disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 806 also includes an integrated circuit die packaged within the communication chip 806. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more thin film transistors having double gates, in accordance with implementations of embodiments of the disclosure.

In further implementations, another component housed within the computing device 800 may contain an integrated circuit die that includes one or more thin film transistors having double gates, in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device 800 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 800 may be any other electronic device that processes data.

Thus, embodiments described herein include double gated thin film transistors.

The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example Embodiment 1

An integrated circuit structure includes an insulator layer above a substrate. A first gate electrode is on the insulator layer, the first gate electrode having a non-planar feature. A first gate dielectric is on and conformal with the non-planar feature of the first gate electrode. A channel material layer is on and conformal with the first gate dielectric. A second gate dielectric is on and conformal with the channel material layer. A second gate electrode is on and conformal with the second gate dielectric. A first source or drain region is coupled to the channel material layer at a first side of the first gate dielectric. A second source or drain region is coupled to the channel material layer at a second side of the first gate dielectric.

Example Embodiment 2

The integrated circuit structure of claim 1, wherein the second gate electrode has a lateral width between the first source or drain region and the second source or drain region the same as a lateral width of the first gate electrode between the first source or drain region and the second source or drain region.

Example Embodiment 3

The integrated circuit structure of claim 1, wherein the second gate electrode has a lateral width between the first source or drain region and the second source or drain region greater than a lateral width of the first gate electrode between the first source or drain region and the second source or drain region.

Example Embodiment 4

The integrated circuit structure of claim 1, wherein the second gate electrode has a lateral width between the first source or drain region and the second source or drain region less than a lateral width of the first gate electrode between the first source or drain region and the second source or drain region.

Example Embodiment 5

The integrated circuit structure of claim 1, 2, 3 or 4, wherein the first gate electrode extends beyond the non-planar feature along the insulator layer, and the integrated circuit structure further includes a second insulator layer on the portion of the first gate electrode that extends beyond the non-planar feature along the insulator layer, the second insulator layer between the second gate electrode and the portion of the first gate electrode that extends beyond the non-planar feature along the insulator layer.

Example Embodiment 6

The integrated circuit structure of claim 1, 2, 3, 4 or 5, wherein the first gate electrode is electrically independent from the second gate electrode.

Example Embodiment 7

The integrated circuit structure of claim 1, 2, 3, 4 or 5, wherein the first gate electrode is electrically coupled to the second gate electrode.

Example Embodiment 8

The integrated circuit structure of claim 1, 2, 3, 4, 5, 6 or 7, wherein the first and second source or drain regions are continuous with the channel material layer.

Example Embodiment 9

The integrated circuit structure of claim 1, 2, 3, 4, 5, 6, 7 or 8, wherein channel material layer includes a semiconducting oxide material.

Example Embodiment 10

The integrated circuit structure of claim 1, 2, 3, 4, 5, 6, 7 or 8, wherein channel material layer includes polycrystalline silicon.

Example Embodiment 11

An integrated circuit structure includes an insulator layer above a substrate. A first gate electrode is on the insulator layer, the first gate electrode having a plurality of fins, individual one of the plurality of fins continuous with one another. A first gate dielectric is on and conformal with the first gate electrode. A channel material layer is on and conformal with the first gate dielectric. A second gate dielectric is on and conformal with a portion of the channel material layer. A second gate electrode is on and conformal with the second gate dielectric. A first source or drain region is coupled to the channel material layer at a first side of the second gate electrode. A second source or drain region is coupled to the channel material layer at a second side of the second gate electrode.

Example Embodiment 12

The integrated circuit structure of claim 11, wherein the first gate electrode is electrically independent from the second gate electrode.

Example Embodiment 13

The integrated circuit structure of claim 11, wherein the first gate electrode is electrically coupled to the second gate electrode.

Example Embodiment 14

The integrated circuit structure of claim 11, 12 or 13, wherein the first and second source or drain regions are continuous with the channel material layer.

Example Embodiment 15

The integrated circuit structure of claim 11, 12, 13 or 14, wherein channel material layer includes a semiconducting oxide material.

Example Embodiment 16

The integrated circuit structure of claim 11, 12, 13 or 14, wherein channel material layer includes polycrystalline silicon.

Example Embodiment 17

An integrated circuit structure includes an insulator layer above a substrate. A first gate electrode is on the insulator layer, the first gate electrode having one or more fins. A first gate dielectric is on and conformal with the first gate electrode. A channel material layer is on and conformal with the first gate dielectric. A second gate dielectric is on and conformal with a portion of the channel material layer. A second gate electrode is on and conformal with the second gate dielectric. A source region is coupled to the channel material layer at a first side of the second gate electrode, the source region having a first conductivity type. A drain region is coupled to the channel material layer at a second side of the second gate electrode, the drain region having a second conductivity type opposite the first conductivity type.

Example Embodiment 18

The integrated circuit structure of claim 17, wherein the first conductivity type is p-type, and the second conductivity type is n-type.

Example Embodiment 19

The integrated circuit structure of claim 17, wherein the first conductivity type is n-type, and the second conductivity type is p-type.

Example Embodiment 20

The integrated circuit structure of claim 17, 18 or 19, wherein the first gate electrode is electrically independent from the second gate electrode.

Example Embodiment 21

The integrated circuit structure of claim 17, 18 or 19, wherein the first gate electrode is electrically coupled to the second gate electrode.

Example Embodiment 22

The integrated circuit structure of claim 17, 18, 19, 20 or 21, wherein the first and second source or drain regions are continuous with the channel material layer.

Example Embodiment 23

The integrated circuit structure of claim 17, 18, 19, 20, 21 or 22, wherein channel material layer includes a semiconducting oxide material.

Example Embodiment 24

The integrated circuit structure of claim 17, 18, 19, 20, 21 or 22, wherein channel material layer includes polycrystalline silicon. 

What is claimed is:
 1. An integrated circuit structure, comprising: an insulator layer above a substrate; a first gate electrode on the insulator layer, the first gate electrode having a non-planar feature; a first gate dielectric on and conformal with the non-planar feature of the first gate electrode; a channel material layer on and conformal with the first gate dielectric; a second gate dielectric on and conformal with the channel material layer; a second gate electrode on and conformal with the second gate dielectric; a first source or drain region coupled to the channel material layer at a first side of the first gate dielectric; and a second source or drain region coupled to the channel material layer at a second side of the first gate dielectric.
 2. The integrated circuit structure of claim 1, wherein the second gate electrode has a lateral width between the first source or drain region and the second source or drain region the same as a lateral width of the first gate electrode between the first source or drain region and the second source or drain region.
 3. The integrated circuit structure of claim 1, wherein the second gate electrode has a lateral width between the first source or drain region and the second source or drain region greater than a lateral width of the first gate electrode between the first source or drain region and the second source or drain region.
 4. The integrated circuit structure of claim 1, wherein the second gate electrode has a lateral width between the first source or drain region and the second source or drain region less than a lateral width of the first gate electrode between the first source or drain region and the second source or drain region.
 5. The integrated circuit structure of claim 1, wherein the first gate electrode extends beyond the non-planar feature along the insulator layer, the integrated circuit structure further comprising: a second insulator layer on the portion of the first gate electrode that extends beyond the non-planar feature along the insulator layer, the second insulator layer between the second gate electrode and the portion of the first gate electrode that extends beyond the non-planar feature along the insulator layer.
 6. The integrated circuit structure of claim 1, wherein the first gate electrode is electrically independent from the second gate electrode.
 7. The integrated circuit structure of claim 1, wherein the first gate electrode is electrically coupled to the second gate electrode.
 8. The integrated circuit structure of claim 1, wherein the first and second source or drain regions are continuous with the channel material layer.
 9. The integrated circuit structure of claim 1, wherein channel material layer comprises a semiconducting oxide material.
 10. The integrated circuit structure of claim 1, wherein channel material layer comprises polycrystalline silicon.
 11. An integrated circuit structure, comprising: an insulator layer above a substrate; a first gate electrode on the insulator layer, the first gate electrode having a plurality of fins, individual one of the plurality of fins continuous with one another; a first gate dielectric on and conformal with the first gate electrode; a channel material layer on and conformal with the first gate dielectric; a second gate dielectric on and conformal with a portion of the channel material layer; a second gate electrode on and conformal with the second gate dielectric; a first source or drain region coupled to the channel material layer at a first side of the second gate electrode; and a second source or drain region coupled to the channel material layer at a second side of the second gate electrode.
 12. The integrated circuit structure of claim 11, wherein the first gate electrode is electrically independent from the second gate electrode.
 13. The integrated circuit structure of claim 11, wherein the first gate electrode is electrically coupled to the second gate electrode.
 14. The integrated circuit structure of claim 11, wherein the first and second source or drain regions are continuous with the channel material layer.
 15. The integrated circuit structure of claim 11, wherein channel material layer comprises a semiconducting oxide material.
 16. The integrated circuit structure of claim 11, wherein channel material layer comprises polycrystalline silicon.
 17. An integrated circuit structure, comprising: an insulator layer above a substrate; a first gate electrode on the insulator layer, the first gate electrode having one or more fins; a first gate dielectric on and conformal with the first gate electrode; a channel material layer on and conformal with the first gate dielectric; a second gate dielectric on and conformal with a portion of the channel material layer; a second gate electrode on and conformal with the second gate dielectric; a source region coupled to the channel material layer at a first side of the second gate electrode, the source region having a first conductivity type; and a drain region coupled to the channel material layer at a second side of the second gate electrode, the drain region having a second conductivity type opposite the first conductivity type.
 18. The integrated circuit structure of claim 17, wherein the first conductivity type is p-type, and the second conductivity type is n-type.
 19. The integrated circuit structure of claim 17, wherein the first conductivity type is n-type, and the second conductivity type is p-type.
 20. The integrated circuit structure of claim 17, wherein the first gate electrode is electrically independent from the second gate electrode.
 21. The integrated circuit structure of claim 17, wherein the first gate electrode is electrically coupled to the second gate electrode.
 22. The integrated circuit structure of claim 17, wherein the first and second source or drain regions are continuous with the channel material layer.
 23. The integrated circuit structure of claim 17, wherein channel material layer comprises a semiconducting oxide material.
 24. The integrated circuit structure of claim 17, wherein channel material layer comprises polycrystalline silicon. 